Cache memories may be used for temporarily storing information read from main memory and to be written to main memory. Cache memories are typically smaller than main memory and can store only a portion of the information stored in main memory. Cache memories are typically configured to provide cached information responsive to a read request faster than main memory can provide the information. If requested information is present in the cache memory, it can be provided much sooner than if the information is read from main memory. Similarly, information may be written to cache memory in less time than writing the information to main memory. The cached information will need to be written to memory eventually, for example, upon eviction of the cached information, but utilizing the cache for writing information allows for fast writing of the information.
Cache memories are typically organized into cache lines in which information read from main memory is stored or information to be written to main memory is stored. In caching information in cache memory, an entire cache line of information is read from memory, even if only a portion of the entire cache line of information is needed. When writing information from cache memory to main memory, the entire cache line of information is written-back even if only a portion of the entire cache line of information needs to be updated in main memory. As a result, there are often many more memory transactions between cache memory and main memory than needed to read requested information into cache or to write information to main memory. The excess memory transactions consume power, reduce performance, and with some types of main memory, result in unnecessary wear of the memory.
Recently, DRAM main memory system designs have moved towards independent control of individual DRAM chips, rather than lock-step control of several chips in parallel. This facilitates transaction sizes as small as 8 Bytes, whereas the current minimum is 64 Bytes. Accessing fewer chips results in less row activation power (a problem called over-fetch). It may be desirable to allow a data processing apparatus to take advantage of such memory systems, while currently the access granularity is fixed to a large size.